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Enhanced Synchronous Serial Interface
(ESSI)
7
The ESSI provides a full-duplex serial port for serial communication with a variety of serial
devices, including one or more industry-standard codecs, other DSPs, microprocessors, and
peripherals. The ESSI consists of independent transmitter and receiver sections and a common
ESSI clock generator. There are two independent and identical ESSIs in the DSP56311: ESSI0
and ESSI1. For simplicity, a single generic ESSI is described here. The ESSI block diagram is
shown in Figure 7-1 . This interface is synchronous because all serial transfers are synchronized
to one clock.
GDB
DDB
RSMA
RSMB
TSMA
RCLK
TCLK
RX SHIFT REG
RX
TX0 SHIFT REG
SRD
STD
TSMB
TX0
CRA
TX1 SHIFT REG
SC0
CRB
TSR
TX1
TX2 SHIFT
SC1
Interrupts
SSISR
TX2
Clock/Frame Sync Generators and Control Logic
SC2
SCK
Figure 7-1. ESSI Block Diagram
This synchronous interface should not be confused with the asynchronous channels mode of the
ESSI, in which separate clocks are used for the receiver and transmitter. In that mode, the ESSI is
still a synchronous device because all transfers are synchronized to these clocks. Pin notations for
the generic ESSI refer to the analogous pin of ESSI0 ( PCx ) and ESSI1 ( PDx ).
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
7-1
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